An FPGA-Based Hardware-in-the-Loop Simulator for Multilevel Converter Systems

This paper presents an FPGA-based real-time simulator, for multilevel converter systems, that is primarily intended for hardware-in-the-loop (HIL) testing applications. The proposed simulator utilizes a customized hardware architecture, as the computational engine, that maps the solution algorithm of the power electronic system under consideration. The designed computational engine enables the use of a simulation timestep in the range of tens to few hundred nanoseconds. Thus eliminating the need for corrective algorithms, to account for the errors arising from the inter-simulation time-step switching phenomenon associated with HIL testing, without compromising the accuracy or the numerical stability. The simulator is tested and its HIL capability verified based on the closed-loop testing of the controller platform for a three-level neutral-point clamped (NPC) converter.